A flash memory device may be programmed and erased by storing charges in a floating gate and by discharging the charges stored in the floating gate into a channel using a tunneling effect. Such a program and erase system may provide improved data retention characteristics. In addition, since flash memory devices may offer advantages such as higher integration, lower power consumption, and/or greater durability against external impact, they may be increasingly used as auxiliary memory devices, for example, in a mobile apparatus and/or other applications.
FIG. 1 is a cross-sectional view illustrating a conventional cell structure of a flash memory device. Referring to FIG. 1, the conventional flash memory cell includes a control gate CG, a floating gate FG, and a source and a drain formed in a bulk substrate or a p-well.
A channel may be defined in the bulk substrate or the p-well between the drain and the source. Between the control gate CG and the floating gate FG, a dielectric layer is formed, which may include an oxide layer/a nitride layer/an oxide (ONO) layer having a relatively high capacitance. Also a tunnel oxide layer having a predetermined configuration that is suitable for Fowler-Nordheim (F-N) tunneling is formed between the floating gate FG and the bulk substrate. In such a cell structure, there may be a dielectric capacitance (CONO) due to the dielectric layer between the control gate CG and the floating gate FG, and a tunnel capacitance (Ctun) due to the tunnel oxide layer between the floating gate FG and the p-well. The voltage of the floating gate FG may be determined by a coupling ratio between a word line voltage VWL applied to the control gate CG and the capacitances CONO and Ctun. In other words, the word line voltage VWL for the program, erase, and/or read operations may be divided by the capacitances. Also, the dielectric capacitance CONO may include a capacitance component due to adjacent transistors, as well as the capacitance between the gates CG and FG. Likewise, the tunnel capacitance Ctun may include a capacitance component due to the adjacent transistors, as well as the capacitance between the floating gate FG and the bulk substrate. As such, the electric field between the floating gate FG and the bulk substrate (or the p-well) inducing the F-N tunneling in a programming operation may depend on the word line voltage VWL divided according to the magnitudes of the dielectric capacitance CONO and the tunnel capacitance Ctun. A voltage Vtun applied between the floating gate FG and the bulk may be represented by Eq. (1) below.Vtun=VWL×αcouple  Eq. (1)
where, αcouple denotes a coupling ratio.
Further, the coupling ratio αcouple may be represented as Eq. (2).
                              α          couple                =                              C            ONO                                              C              ONO                        +                          C              tun                                                          Eq        .                                  ⁢                  (          2          )                    
Based on Eqs. 1 and 2, the magnitude of the tunneling voltage Vtun (i.e., the floating gate voltage), which may effect the F-N tunneling in the programming operation, may largely depend upon the magnitude of the coupling ratio αcouple. Also, it may be difficult and/or impossible to fabricate memory cells in the same string/row of a NAND flash memory all having the same coupling ratio αcouple. More particularly, cells directly adjacent to a string select line (SSL) and/or a ground select line (GSL) in each string may have higher or lower coupling ratios than the coupling ratios of other cells. For example, because the capacitance of each cell may also incorporate a capacitance component of an adjacent cell, the capacitance component between cells in the string structure may be different from the capacitance component between the outermost cells of the string structure and the select transistors. Therefore, although the same voltage may be applied to the respective word lines, the floating gate voltage Vtun (i.e., the tunneling voltage) induced in cells adjacent to the SSL/GSL may be different from the floating gate voltage Vtun induced to other cells. Considering that program speed may depend on the magnitude of the floating gate voltage Vtun, the program speed of the memory cells may vary with the location of the respective word lines.